In MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors), subthreshold conduction refers to the flow of current between the source and drain terminals when the transistor is operating in its "off" state, i.e., when the gate-source voltage (Vgs) is below the threshold voltage (Vth) required to turn it "on." This phenomenon occurs due to the presence of a thin insulating layer (oxide) between the gate and the channel.
When the MOSFET is biased with a Vgs below the threshold voltage, a small amount of leakage current, known as subthreshold leakage or subthreshold current (Isub), flows through the channel. This leakage current arises because there is a finite probability that some charge carriers (electrons or holes) can tunnel through the thin gate oxide barrier, despite the lack of a significant gate voltage to attract them.
The impact of subthreshold conduction on power consumption in MOSFETs can be significant, especially in modern integrated circuits that contain a large number of transistors. There are two primary reasons for this:
Standby Power: In digital circuits, MOSFETs are often used to implement switches and logic gates. When a logic gate is in its "off" state (Vgs < Vth), it should ideally consume negligible power. However, due to subthreshold conduction, a small but non-zero amount of current continues to flow between the source and drain. In a large-scale integrated circuit with millions or billions of transistors, the cumulative subthreshold leakage from all these transistors can lead to a significant standby power consumption, also known as leakage power.
Scaling Challenges: As technology nodes shrink and transistors become smaller, subthreshold leakage becomes more pronounced. This phenomenon poses a major challenge for semiconductor manufacturers as they strive to reduce the feature size and increase the transistor density. Leakage power can become a significant fraction of the overall power consumption, reducing the gains in power efficiency achieved through other means like dynamic power management or voltage scaling.
To mitigate the impact of subthreshold conduction on power consumption, semiconductor manufacturers and circuit designers use various techniques. Some of these include:
Threshold Voltage Engineering: Modifying the transistor's threshold voltage by adjusting the doping levels in the channel region to control subthreshold leakage.
Power Gating: Shutting down the power supply to specific circuit blocks or portions of a chip during idle or standby periods to minimize leakage power.
Subthreshold Leakage Reduction Techniques: Using design and architectural optimizations to reduce subthreshold leakage, such as reverse body biasing, multi-threshold voltage designs, and stacking transistors in series.
Innovative Transistor Structures: Exploring new transistor architectures that reduce or eliminate subthreshold leakage, such as tunnel FETs (TFETs), which rely on tunneling rather than thermal activation for conduction.
Overall, managing subthreshold conduction is crucial in modern semiconductor design to improve power efficiency and extend battery life in portable devices while enabling the continued scaling of integrated circuits.