A decade counter is a digital electronic circuit that counts in decimal (base-10) format, advancing through a sequence of ten different states. It is commonly used in digital circuits to divide a clock frequency by 10 and perform various counting applications. The decade counter typically consists of flip-flops and logic gates arranged in a specific configuration.
Let's take a look at the operation of a simple asynchronous decade counter using D flip-flops (DFFs):
Components: The basic building block of a decade counter is the D flip-flop. A D flip-flop has two inputs: D (data input) and CLK (clock input) and one output, Q (output). When a clock edge (rising or falling edge) is detected, the D flip-flop stores the value of the D input and outputs it at the Q output. A D flip-flop can be positive edge-triggered or negative edge-triggered, meaning it captures the input value at the rising or falling edge of the clock signal, respectively.
Configuration: To build a 4-bit decade counter (counting from 0 to 9), we will cascade four D flip-flops (DFFs) together. The output of each DFF is connected to the clock input of the next DFF in the chain. The D input of each DFF is set to a specific value that determines the counting sequence.
Counting sequence: The counting sequence for the decade counter is as follows: 0000, 0001, 0010, 0011, 0100, 0101, 0110, 0111, 1000, and 1001. These are the binary representations of the decimal numbers from 0 to 9.
Operation:
Initially, all the DFFs are reset to 0, and the outputs (Q) of all the flip-flops are 0.
When the clock signal starts oscillating, the first DFF (D0) starts counting based on the clock's edge. The D0 input is connected to logic 1 (high), so it will count when the clock's edge occurs.
The Q output of D0 will change from 0 to 1 on the first clock edge.
The Q output of D0 is connected to the clock input of the second DFF (D1). The second DFF will count when the clock's edge occurs, transitioning from 0 to 1.
The Q output of D1 is connected to the clock input of the third DFF (D2), and the process continues.
The Q output of D2 is connected to the clock input of the fourth DFF (D3).
When the fourth DFF (D3) counts from 0 to 1 on the next clock edge, it completes the counting sequence (0000 to 1001).
At this point, all DFFs will reset to 0, and the counting process starts again.
Reset: Decade counters usually include a reset input, which sets all the flip-flop outputs to 0, forcing the counter to restart from the initial value.
By connecting multiple D flip-flops in this manner, a decade counter can efficiently count from 0 to 9 and repeat the counting process in a continuous loop.